Intel Celeron M 440 1.86GHz BX80538440 Data Sheet

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Regulator solutions need to provide bulk capacitance with a low effective series resistance (ESR) 

and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the 

large current swings when the part is powering on, or entering/exiting low-power states, must be 
provided by the voltage regulator solution. For more details on decoupling recommendations, 

please refer to the platform design guides. Intel strongly recommends that the layout and 

decoupling recommendations in the platform design guides be followed. 

Intel

 

Celeron M processors integrate signal termination on the die as well as incorporate high- 

frequency decoupling capacitance on the processor package. Decoupling must also be provided by 
the system motherboard for proper AGTL+ bus operation. For more information, refer to the 

platform design guides.

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. 

As in previous generation processors, the Intel Celeron M processor core frequency is a multiple of 

the BCLK[1:0] frequency. In regards to processor clocking, the Intel Celeron M processor uses a 
differential clocking implementation.

The processor uses six voltage identification pins, VID[5:0], to support automatic selection of 

power supply voltages. The VID pins for the processor are CMOS outputs driven by the processor 

VID circuitry. 

 specifies the voltage level corresponding to the state of VID[5:0]. A 1 in this 

refers to a high-voltage level and a 0 refers to low-voltage level.