HP A2Y15AV User Manual
Processor Configuration Registers
132
Datasheet, Volume 2
2.7
PCI Device 1 Function 0–2 Extended Configuration
Registers
Table 2-10. PCI Device 1 Function 0–2 Extended Configuration Register Address Map
Address
Offset
Register
Symbol
Register Name
Reset Value
Access
0–103h
RSVD
Reserved
0h
RO
104–107h
PVCCAP1
Port VC Capability Register 1
00000000h
RO
108–10Bh
PVCCAP2
Port VC Capability Register 2
00000000h
RO
10C–10Dh
PVCCTL
Port VC Control
0000h
RW, RO
10E–10Fh
RSVD
Reserved
0h
RO
110–113h
VC0RCAP
VC0 Resource Capability
00000001h
RO
114–117h
VC0RCTL
VC0 Resource Control
800000FFh
RO, RW
118–119h
RSVD
Reserved
0h
RO
11A–11Bh
VC0RSTS
VC0 Resource Status
0002h
RO-V
11C–207h
RSVD
Reserved
0h
RO
208–20Bh
PEG_TC
PCI Express Completion Time-out
00010005h
RW
20C–D9Fh
RSVD
Reserved
02000100h
RO, RW-O
DA0–DA3h
EQCTL0_1
Lane 0/1 Equalization Control Register
07080708h
RW
DA4–DA7h
EQCTL2_3
Lane 2/3 Equalization Control Register
07080708h
RW
DA8–DABh
EQCTL4_5
Lane 4/5 Equalization Control Register
07080708h
RW
DAC–DAFh
EQCTL6_7
Lane 6/7 Equalization Control Register
07080708h
RW
DB0–DB3h
EQCTL8_9
Lane 8/9 Equalization Control Register
07080708h
RW
DB4–DB7h
EQCTL10_11
Lane 10/11 Equalization Control
Register
07080708h
RW
DB8–DBBh
EQCTL12_13
Lane 12/13 Equalization Control
Register
07080708h
RW
DBC–DBFh
EQCTL14_15
Lane 14/15 Equalization Control
Register
07080708h
RW
DC0–DD7h
RSVD
Reserved
0h
RO
DD8–DDBh
EQCFG
Equalization Configuration Register
F9404400h
RW