HP A2Y15AV User Manual
Datasheet, Volume 2
301
Processor Configuration Registers
2.19.6
GT_PERF_STATUS—GT Performance Status Register
This register provides the P-state encoding for the Secondary Power Plane’s current PLL
frequency and the current VID.
frequency and the current VID.
2.19.7
RP_STATE_LIMITS—RP-State Limitations Register
This register allows software to limit the maximum base frequency for the Integrated
Graphics Engine (GT) allowed during run-time.
Graphics Engine (GT) allowed during run-time.
B/D/F/Type:
0/0/0/MCHBAR PCU
Address Offset:
5948–594Bh
Reset Value:
00000000h
Access:
RO-V
Size:
32 bits
BIOS Optimal Default
0000h
Bit
Access
Reset
Value
RST/
PWR
Description
31:16
RO
0h
Reserved (RSVD)
15:8
RO-V
00h
Uncore
RP-State Ratio (RP_STATE_RATIO)
This field provides the ratio of the current RP-state.
This field provides the ratio of the current RP-state.
7:0
RO-V
00h
Reserved (RSVD)
B/D/F/Type:
0/0/0/MCHBAR PCU
Address Offset:
5994–5997h
Reset Value:
000000FFh
Access:
RW
Size:
32 bits
BIOS Optimal Default
000000h
Bit
Access
Reset
Value
RST/
PWR
Description
31:8
RO
0h
Reserved (RSVD)
7:0
RW
FFh
Uncore
RP-State Limit (RPSTT_LIM)
This field indicates the maximum base frequency limit for the
This field indicates the maximum base frequency limit for the
Integrated Graphics Engine (GT) allowed during run-time.