Intel i5-2540M FF8062700839209 User Manual
Product codes
FF8062700839209
Datasheet
13
Features Summary
• Up to 32 simultaneous open pages, 16 per channel (assuming 4 Ranks of 8 Bank
Devices)
• Memory organizations:
— Single-channel modes
— Dual-channel modes - Intel® Flex Memory Technology:
— Dual-channel modes - Intel® Flex Memory Technology:
Dual-channel symmetric (Interleaved)
Dual-channel asymmetric
Dual-channel asymmetric
• Command launch modes of 1n/2n
• Partial Writes to memory using Data Mask (DM) signals
• On-Die Termination (ODT)
• Intel® Fast Memory Access (Intel® FMA):
• Partial Writes to memory using Data Mask (DM) signals
• On-Die Termination (ODT)
• Intel® Fast Memory Access (Intel® FMA):
— Just-in-Time Command Scheduling
— Command Overlap
— Out-of-Order Scheduling
— Command Overlap
— Out-of-Order Scheduling
1.3.2
PCI Express*
• One, 16-lane PCI Express* port intended for Graphics Attach, fully-compliant to the
PCI Express Base Specification, Revision 2.0.
• PCI Express Port 0 is mapped to PCI Device 1 (PEG 0).
• Gen1 (2.5 GT/s) PCI Express frequency is supported.
• Gen1 Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per
• Gen1 (2.5 GT/s) PCI Express frequency is supported.
• Gen1 Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per
pair of 250 MB/s given the 8b/10b encoding used to transmit data across this
interface. This also does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 4 GB/s in each direction
simultaneously, for an aggregate of 8 GB/s when x16 Gen 1.
• Hierarchical PCI-compliant configuration mechanism for downstream devices.
• Traditional PCI style traffic (asynchronous snooped, PCI ordering).
• PCI Express extended configuration space. The first 256 bytes of configuration
• Traditional PCI style traffic (asynchronous snooped, PCI ordering).
• PCI Express extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as “extended configuration space”.
• PCI Express Enhanced Access Mechanism. Accessing the device configuration space
in a flat memory mapped fashion.
• Automatic discovery, negotiation, and training of link out of reset.
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering).
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering).
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in
Virtual Channel 0:
— DMI -> PCI Express Port 0
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros).