Intel i5-2540M FF8062700839209 User Manual

Product codes

FF8062700839209

Power Management

Datasheet

Entry and exit of the C-States at the thread and core level are shown in

While individual threads can request low power C-states, power saving actions only

take place once the core C-state is resolved. Core C-states are automatically resolved

by the processor. For thread and core C-states, a transition to and from C0 is required

before entering any other C-state.

NOTE:If enabled, the core C-state will be C1E if all actives cores have also resolved a

core C1 state or higher

4.2.3

Requesting Low-Power Idle States

The primary software interfaces for requesting low power idle states are through the

MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).

However, software may make C-state requests using the legacy method of I/O reads

from the ACPI-defined processor clock control registers, referred to as P_LVLx. This

method of requesting C-states provides legacy support for operating systems that

initiate C-state transitions via I/O reads.

For legacy operating systems, P_LVLx I/O reads are converted within the processor to

the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result in

I/O reads to the system. The feature, known as I/O MWAIT redirection, must be

enabled in the BIOS.

Figure 10.

Thread and Core C-State Entry and Exit

C1E

MWAIT(C1), HLT

MWAIT(C6),

P_LVL3 I/O Read

MWAIT(C3),

P_LV2 I/O Read

MWAIT(C1), HLT

(C1E Enabled)

Table 14.

Coordination of Thread Power States at the Core Level

Processor

Core

C-State

Thread 1

read 0