Intel i5-2540M FF8062700839209 User Manual

Datasheet

49

PSI# and DPRSLPVR# are signals used to optimize VR efficiency over a wide power 

range depending on amount of activity within the processor core. The PSI# signal is 

utilized by the processor core to:

• Improve intermediate and light load efficiency of the voltage regulator when the 

processor is active (P-states).

• Optimize voltage regulator efficiency in very low power states. Assertion of 

DPRSLPVR# indicates that the processor core is in a C6 low power state.

The VR efficiency gains result in overall platform power savings and extended battery 

life. 

The main memory is power managed during normal operation and in low-power ACPI 

Cx states.

Any system memory (SM) interface signal that goes to a memory module connector in 

which it is not connected to any actual memory devices (such as SO-DIMM connector is 

unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM 

signals are:

• Reduced power consumption.
• Reduced possible overshoot/undershoot signal quality issues seen by the processor 

I/O buffer receivers caused by reflections from potentially un-terminated 

transmission lines.

When a given rank is not populated, the corresponding chip select and CKE signals are 

not driven.

At reset, all rows must be assumed to be populated, until it can be proven that they are 

not populated. This is due to the fact that when CKE is tristated with an SO-DIMM 

present, the SO-DIMM is not guaranteed to maintain data integrity.

The processor implements extensive support for power management on the SDRAM 

interface. There are four SDRAM operations associated with the Clock Enable (CKE) 

signals, which the SDRAM controller supports. The processor drives four CKE pins to 

perform these operations.

During power-up, CKE is the only input to the SDRAM that has its level is recognized 

(other than the DDR3 reset pin) once power is applied. It must be driven LOW by the 

DDR controller to make sure the SDRAM components float DQ and DQS during power-

up. CKE signals remain LOW (while any reset is active) until the BIOS writes to a 

configuration register. Using this method, CKE is guaranteed to remain inactive for 

much longer than the specified 200 micro-seconds after power and clocks to SDRAM 

devices are stable.