Intel i5-2540M FF8062700839209 User Manual

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Datasheet

BPM#[7:0]

Breakpoint and Performance Monitor 
Signals: Outputs from the processor that 
indicate the status of breakpoints and 
programmable counters used for monitoring 
processor performance.

I/O 

GTL

CFG[17:0]

Configuration Signals:
The CFG signals have a default value of '1' if 
not terminated on the board. 
CFG[2:0] - Reserved configuration pins. Test 
points may be placed on these pins on a 
common motherboard design.
CFG[3] – PCI Express* Static Lane 
Numbering Reversal. Lane Reversal will be 
applied across all 16 Lanes.

•  1: No lane reversal
•  0: Reversal

CFG[4] - Embedded DisplayPort Detection: 
This is used to detect the presence of a 
device on the Embedded DisplayPort.
CFG[17:5] - Reserved configuration pins. 
Note: Hardware straps are sampled on the 
asserting edge of VCCPWRGOOD_0 and 
VCCPWRGOOD_1 and latched inside the 
processor.

I

CMOS

COMP0

Impedance compensation must be 
terminated on the system board using a 
precision resistor.

I

A

COMP1

Impedance compensation must be 
terminated on the system board using a 
precision resistor.

I

A

COMP2

Impedance compensation must be 
terminated on the system board using a 
precision resistor.

I

A

COMP3

Impedance compensation must be 
terminated on the system board using a 
precision resistor.

I

A

DBR#

Debug Reset: Used only in systems where 
no debug port is implemented on the system 
board. DBR# is used by a debug port 
interposer so that an in-target probe can 
drive system reset. This signal only routes 
through the package and does not connect to 
the processor silicon itself.

O