Intel i5-2540M FF8062700839209 User Manual

Datasheet

91

NOTES:
1.

Refer to 

 for signal description details.

2.

SA and SB refer to DDR3 Channel A and DDR3 Channel B.

3.

These signals are only applicable for the ARD BGA package

4.

These signals are only applicable for the rPGA988A package.

All Control Sideband Asynchronous signals are required to be asserted/deasserted for 
at least eight BCLKs in order for the processor to recognize the proper signal state. See 

Due to the voltage levels supported by other components in the Test Access Port (TAP) 

logic, Intel recommends the processor be first in the TAP chain, followed by any other 

components within the system. A translation buffer should be used to connect to the 

rest of the chain unless one of the other components is capable of accepting an input of 

the appropriate voltage. Two copies of each signal may be required with each driving a 

different voltage level. 

Single Ended

(aa)

Analog Input

GFX_IMON

Single Ended

(ab)

CMOS Output

GFX_VID[6:0], GFX_VR_EN, GFX_DPRSLPVR

Differential

(ac)

PCI Express Input

PEG_RX[15:0], PEG_RX#[15:0]

Differential

(ad)

PCI Express Output

PEG_TX[15:0], PEG_TX#[15:0]

Single Ended

(ae)

Analog Input

PEG_ICOMP0, PEG_ICOMPI, PEG_RCOMP0, 
PEG_RBIAS

Differential

(af)

DMI Input

DMI_RX[3:0], DMI_RX#[3:0]

Differential

(ag)

DMI Output

DMI_TX[3:0], DMI_TX#[3:0]

Single Ended

(ah)

CMOS Input

FDI_FSYNC[1:0], FDI_LSYNC[1:0], FDI_INT

Differential

(ai)

Analog Output

FDI_TX[7:0], FDI_TX#[7:0]