NEC Intel Xeon E5-2430 N8101-563F User Manual

Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families

25

Datasheet Volume One

This chapter describes the interfaces supported by the processor. 

The Integrated Memory Controller (IMC) supports DDR3 protocols with four 
independent 64-bit memory channels with 8 bits of ECC for each channel (total of 
72-bits) and supports 1 to 3 DIMMs per channel depending on the type of memory 
installed. The type of memory supported by the processor is dependent on the target 
platform:

• Intel® Xeon® processor E5 product family-based platforms support:

— ECC registered DIMMs: with a maximum of three DIMMs per channel allowing 

up to eight

 

device ranks per channel.

— ECC and non-ECC unbuffered DIMMs: with a maximum of two DIMMs per 

channel thus allowing up to four device ranks per channel. Support for mixed 

non-ECC with ECC un-buffered DIMM configurations.

The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and 
command signal mode timings on the main memory interface:

• tCL = CAS Latency
• tRCD = Activate Command to READ or WRITE Command delay
• tRP = PRECHARGE Command Period
• CWL = CAS Write Latency
• Command Signal modes = 1n indicates a new command may be issued every clock 

and 2n indicates a new command may be issued every 2 clocks. Command launch 
mode programming depends on the transfer rate and memory configuration.