NEC Intel Xeon E5-2430 N8101-563F User Manual
Product codes
N8101-563F
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
31
Datasheet Volume One
2.5.1.1
Thermal Management
Processor fan speed control is managed by comparing Digital Thermal Sensor (DTS)
thermal readings acquired via PECI against the processor-specific fan speed control
reference point, or T
thermal readings acquired via PECI against the processor-specific fan speed control
reference point, or T
CONTROL
. Both T
CONTROL
and DTS thermal readings are accessible
via the processor PECI client. These variables are referenced to a common
temperature, the TCC activation point, and are both defined as negative offsets from
that reference.
temperature, the TCC activation point, and are both defined as negative offsets from
that reference.
PECI-based access to the processor package configuration space provides a means for
Baseboard Management Controllers (BMCs) or other platform management devices to
actively manage the processor and memory power and thermal features. Details on the
list of available power and thermal optimization services can be found in
Baseboard Management Controllers (BMCs) or other platform management devices to
actively manage the processor and memory power and thermal features. Details on the
list of available power and thermal optimization services can be found in
2.5.1.2
Platform Manageability
PECI allows read access to certain error registers in the processor MSR space and
status monitoring registers in the PCI configuration space within the processor and
downstream devices. Details are covered in subsequent sections.
status monitoring registers in the PCI configuration space within the processor and
downstream devices. Details are covered in subsequent sections.
PECI permits writes to certain Memory Controller RAS-related registers in the processor
PCI configuration space. Details are covered in
PCI configuration space. Details are covered in
.
2.5.1.3
Processor Interface Tuning and Diagnostics
The processor Intel® Interconnect Built In Self Test (Intel® IBIST) allows for in-field
diagnostic capabilities in the Intel® QPI and memory controller interfaces. PECI
provides a port to execute these diagnostics via its PCI Configuration read and write
capabilities in the BMC INIT mode. Refer to
diagnostic capabilities in the Intel® QPI and memory controller interfaces. PECI
provides a port to execute these diagnostics via its PCI Configuration read and write
capabilities in the BMC INIT mode. Refer to
for more details.
2.5.2
Client Command Suite
PECI command requires at least one frame check sequence (FCS) byte to ensure
reliable data exchange between originator and client. The PECI message protocol
defines two FCS bytes that are returned by the client to the message originator. The
first FCS byte covers the client address byte, the Read and Write Length bytes, and all
bytes in the write data block. The second FCS byte covers the read response data
returned by the PECI client. The FCS byte is the result of a cyclic redundancy check
(CRC) of each data block.
reliable data exchange between originator and client. The PECI message protocol
defines two FCS bytes that are returned by the client to the message originator. The
first FCS byte covers the client address byte, the Read and Write Length bytes, and all
bytes in the write data block. The second FCS byte covers the read response data
returned by the PECI client. The FCS byte is the result of a cyclic redundancy check
(CRC) of each data block.
2.5.2.1
Ping()
Ping() is a required message for all PECI devices. This message is used to enumerate
devices or determine if a device has been removed, been powered-off, etc. A Ping()
sent to a device address always returns a non-zero Write FCS if the device at the
targeted address is able to respond.
devices or determine if a device has been removed, been powered-off, etc. A Ping()
sent to a device address always returns a non-zero Write FCS if the device at the
targeted address is able to respond.
2.5.2.1.1
Command Format
The Ping() format is as follows:
Write Length: 0x00
Read Length: 0x00