Intel G645 BX80623G645 User Manual

206

Datasheet, Volume 2

This register provides the regular timing parameters in DCLK cycles. 

This register identifies the I/O latency per rank, and I/O compensation (global).

31:24

RO

0h

23:16

RW-L

10h

Four-Activate Window 
This field provides the time frame in which maximum of 4 ACT 

commands to the same rank are allowed. The minimum value is 

4*tRRD; the maximum value is 63 DCLK cycles.

15:12

RW-L

4h

Delay Internal WR to RD Transaction
This field provides the delay from internal WR transaction to 

internal RD transaction. The minimum delay is 4 DCLK cycles, 

whereas the maximum delay is 8 DCLK cycles.

11:8

RO

0h

7:4

RW-L

4h

Minimum Delay From CAS-RD to PRE 
The minimum delay is 4 DCLK cycles; the maximum delay is 8 

DCLK cycles.

3:0

RW-L

4h

Delay Between Two Act Commands
tRRD is the minimum delay between two ACT commands targeted 

to different banks in the same rank. The minimum delay is 4 DCLK 

cycles; the maximum delay is 7 cycles.

31:16

RO

0h

15:12

RW-L

0h

11:8

RW-L

0h

7:4

RW-L

0h

3:0

RW-L

0h