Intel G645 BX80623G645 User Manual
Product codes
BX80623G645
Processor Configuration Registers
22
Datasheet, Volume 2
for managing DMA accesses to addresses above 4 GB. DMA-remapping hardware
implementations on platforms supporting Intel TXT are required to support
protected high-memory region6, if the platform supports main memory above
4 GB.
implementations on platforms supporting Intel TXT are required to support
protected high-memory region6, if the platform supports main memory above
4 GB.
Once the protected low/high memory region registers are configured, bus master
protection to these regions is enabled through the Protected Memory Enable register.
For platforms with multiple DMA-remapping hardware units, each of the DMA-
remapping hardware units must be configured with the same protected memory
regions and enabled.
protection to these regions is enabled through the Protected Memory Enable register.
For platforms with multiple DMA-remapping hardware units, each of the DMA-
remapping hardware units must be configured with the same protected memory
regions and enabled.
2.3.2.4
DRAM Protected Range (DPR)
This protection range only applies to DMA accesses and GMADR translations. It serves a
purpose of providing a memory range that is only accessible to processor streams.
purpose of providing a memory range that is only accessible to processor streams.
The DPR range works independent of any other range, including the PMRC checks in
VT-d. It occurs post any VT-d translation. Therefore, incoming cycles are checked
against this range after the VT-d translation and faulted if they hit this protected range,
even if they passed the VT-d translation.
VT-d. It occurs post any VT-d translation. Therefore, incoming cycles are checked
against this range after the VT-d translation and faulted if they hit this protected range,
even if they passed the VT-d translation.
The system will set up:
• 0 to (TSEG_BASE – DPR size – 1) for DMA traffic
• TSEG_BASE to (TSEG_BASE – DPR size) as no DMA.
• TSEG_BASE to (TSEG_BASE – DPR size) as no DMA.
After some time, software could request more space for not allowing DMA. It will get
some more pages and make sure there are no DMA cycles to the new region. DPR size
is changed to the new value. When it does this, there should not be any DMA cycles
going to DRAM to the new region.
some more pages and make sure there are no DMA cycles to the new region. DPR size
is changed to the new value. When it does this, there should not be any DMA cycles
going to DRAM to the new region.
If there were cycles from a rogue device to the new region, then those could use the
previous decode until the new decode can guarantee PV. No flushing of cycles is
required. On a clock by clock basis proper decode with the previous or new decode
needs to be ensured.
previous decode until the new decode can guarantee PV. No flushing of cycles is
required. On a clock by clock basis proper decode with the previous or new decode
needs to be ensured.
All upstream cycles from 0 to (TSEG_BASE – 1 – DPR size), and not in the legacy holes
(VGA), are decoded to DRAM.
(VGA), are decoded to DRAM.
Because Bus Master cycles can occur when the DPR size is changed, the DPR size needs
to be treated dynamically.
to be treated dynamically.
2.3.2.5
Pre-allocated Memory
Voids of physical addresses that are not accessible as general system memory and
reside within system memory address range (< TOLUD) are created for SMM-mode,
legacy VGA graphics compatibility, and graphics GTT stolen memory. It is the
responsibility of BIOS to properly initialize these regions.
reside within system memory address range (< TOLUD) are created for SMM-mode,
legacy VGA graphics compatibility, and graphics GTT stolen memory. It is the
responsibility of BIOS to properly initialize these regions.