Intel G645 BX80623G645 User Manual
Product codes
BX80623G645
Datasheet, Volume 2
9
2.21.27 IRTA_REG—Interrupt Remapping Table Address Register........................ 292
2.21.28 IVA_REG—Invalidate Address Register ................................................. 293
2.21.29 IOTLB_REG—IOTLB Invalidate Register ................................................ 294
2.21.28 IVA_REG—Invalidate Address Register ................................................. 293
2.21.29 IOTLB_REG—IOTLB Invalidate Register ................................................ 294
Figures
Tables
2-10 PCI Device 2 Configuration Register Address Map ................................................ 130
2-11 Device 2 I/O Register Address Map .................................................................... 142
2-12 PCI Device 6 Register Address Map.................................................................... 143
2-13 PCI Device 6 Extended Configuration Register Address Map .................................. 181
2-14 DMIBAR Register Address Map .......................................................................... 186
2-15 MCHBAR Registers in Memory Controller – Channel 0 Register Address Map ............ 205
2-16 MCHBAR Registers in Memory Controller – Channel 1 Register Address Map ............ 209
2-17 MCHBAR Registers in Memory Controller – Integrated Memory Peripheral Hub ......... 213
2-18 MCHBAR Registers in Memory Controller – Common Register Address Map.............. 214
2-19 Memory Controller MMIO Registers Broadcast Group Register Address Map ............. 218
2-20 Integrated Graphics VT-d Remapping Engine Register Address Map........................ 220
2-21 PCU MCHBAR Register Address Map ................................................................... 255
2-22 PXPEPBAR Register Address Map ....................................................................... 263
2-23 Default PEG/DMI VT-d Remapping Engine Register Address Map ............................ 264
2-11 Device 2 I/O Register Address Map .................................................................... 142
2-12 PCI Device 6 Register Address Map.................................................................... 143
2-13 PCI Device 6 Extended Configuration Register Address Map .................................. 181
2-14 DMIBAR Register Address Map .......................................................................... 186
2-15 MCHBAR Registers in Memory Controller – Channel 0 Register Address Map ............ 205
2-16 MCHBAR Registers in Memory Controller – Channel 1 Register Address Map ............ 209
2-17 MCHBAR Registers in Memory Controller – Integrated Memory Peripheral Hub ......... 213
2-18 MCHBAR Registers in Memory Controller – Common Register Address Map.............. 214
2-19 Memory Controller MMIO Registers Broadcast Group Register Address Map ............. 218
2-20 Integrated Graphics VT-d Remapping Engine Register Address Map........................ 220
2-21 PCU MCHBAR Register Address Map ................................................................... 255
2-22 PXPEPBAR Register Address Map ....................................................................... 263
2-23 Default PEG/DMI VT-d Remapping Engine Register Address Map ............................ 264