Intel G645T CM8062301263701 User Manual
Product codes
CM8062301263701
Datasheet, Volume 2
19
Processor Configuration Registers
2.3.1.2
Legacy Video Area (A_0000h–B_FFFFh)
The legacy 128 KB VGA memory range, frame buffer, (000A_0000h–000B_FFFFh) can
be mapped to IGD (Device 2), to PCI Express (Device 1 or Device 6), and/or to the DMI
Interface. The appropriate mapping depends on which devices are enabled and the
programming of the VGA steering bits. Based on the VGA steering bits, priority for VGA
mapping is constant. The processor always decodes internally mapped devices first.
be mapped to IGD (Device 2), to PCI Express (Device 1 or Device 6), and/or to the DMI
Interface. The appropriate mapping depends on which devices are enabled and the
programming of the VGA steering bits. Based on the VGA steering bits, priority for VGA
mapping is constant. The processor always decodes internally mapped devices first.
Non-SMM-mode processor accesses to this range are considered to be to the Video
Buffer Area as described above.
Buffer Area as described above.
The processor always positively decodes internally mapped devices, namely the IGD
and PCI-Express. Subsequent decoding of regions mapped to PCI Express or the DMI
Interface depends on the Legacy VGA configuration bits (VGA Enable and MDAP). This
region is also the default for SMM space.
and PCI-Express. Subsequent decoding of regions mapped to PCI Express or the DMI
Interface depends on the Legacy VGA configuration bits (VGA Enable and MDAP). This
region is also the default for SMM space.
Compatible SMRAM Address Range (A_0000h–B_FFFFh)
When compatible SMM space is enabled, SMM-mode processor accesses to this range
route to physical system DRAM at 000A_0000h–000B_FFFFh.
route to physical system DRAM at 000A_0000h–000B_FFFFh.
PCI Express and DMI originated cycles to enable SMM space are not allowed and are
considered to be to the Video Buffer Area, if IGD is not enabled as the VGA device. DMI
initiated write cycles are attempted as peer write cycles to a VGA enabled PCIe port.
considered to be to the Video Buffer Area, if IGD is not enabled as the VGA device. DMI
initiated write cycles are attempted as peer write cycles to a VGA enabled PCIe port.
Monochrome Adapter (MDA) Range (B_0000h–B_7FFFh)
Legacy support requires the ability to have a second graphics controller (monochrome)
in the system. Accesses in the standard VGA range are forwarded to IGD, PCI-Express,
or the DMI Interface (depending on configuration bits). Since the monochrome adapter
may be mapped to any of these devices, the processor must decode cycles in the MDA
range (000B_0000h–000B_7FFFh) and forward either to IGD, PCI-Express, or the DMI
Interface. This capability is controlled by the VGA steering bits and the legacy
configuration bit (MDAP bit). In addition to the memory range B0000h to B7FFFh, the
processor decodes I/O cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, and 3BFh and
forwards them to either IGD, PCI-Express, and/or the DMI Interface.
in the system. Accesses in the standard VGA range are forwarded to IGD, PCI-Express,
or the DMI Interface (depending on configuration bits). Since the monochrome adapter
may be mapped to any of these devices, the processor must decode cycles in the MDA
range (000B_0000h–000B_7FFFh) and forward either to IGD, PCI-Express, or the DMI
Interface. This capability is controlled by the VGA steering bits and the legacy
configuration bit (MDAP bit). In addition to the memory range B0000h to B7FFFh, the
processor decodes I/O cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, and 3BFh and
forwards them to either IGD, PCI-Express, and/or the DMI Interface.
PEG 16-bit VGA Decode
In the PCI to PCI Bridge Architecture Specification, Revision 1.2 it is required that 16-
bit VGA decode be a feature.
bit VGA decode be a feature.
When 16-bit VGA decode is disabled, the decode of VGA I/O addresses is performed on
10 lower bits only, essentially mapping also the aliases of the defined I/O addresses.
10 lower bits only, essentially mapping also the aliases of the defined I/O addresses.