Intel G645T CM8062301263701 User Manual

Datasheet, Volume 2

39

— No “pacer” arbitration or TWRR arbitration will occur. Never remaps to different 

port. (PCH takes care of Egress port remapping). The PCH will meter TCm ME 

accesses and Azalia TC1 access bandwidth.

— Internal Graphics GMADR writes and GMADR reads are not supported.

• VCm accesses

— See the DMI2 specification for TC mapping to VCm. VCm access only map to 

Intel ME stolen DRAM. These transactions carry the direct physical DRAM 

address (no redirection or remapping of any kind will occur). This is how the 

PCH management engine accesses its dedicated DRAM stolen space.

— DMI block will decode these transactions to ensure only Intel ME stolen 

memory is targeted, and abort otherwise. 

— VCm transactions will only route non-snoop.
— VCm transactions will not go through VT-d remap tables. 
— The remapbase/remaplimit registers to not apply to VCm transactions.

A0000-BFFFF (VGA)

GMADR

FEE0_0000 – FEEF_FFFF( MSI)

TSEG_BASE

mem writes 

 non-snoop mem write

mem reads 

 invalid transaction

mem writes 

 CPU (IntLogical/IntPhysical)

mem reads 

 Invalid transaction

mem writes 

 peer write (if matching PEG range else invalid)

mem reads 

 Invalid transaction

64GB

REMAPLIMIT

TOLUD

4GB

REMAPBASE

mem writes 

 Route based on SNR bit.

mem reads 

 Route based on SNR bit.

TOM = total physical DRAM

Upstream Initiated VC0 Cycle Memory Map

TOLUD-(Gfx Stolen)-(Gfx GTT stolen)
-(TSEG)

TSEG_BASE - DPR

2TB

mem writes 

 peer write (based on Dev1 VGA en) else invalid

mem reads 

 Invalid transaction

TOUUD