Intel G645 CM8062301262601 User Manual

Datasheet, Volume 2

51

8

RW1C

0b

Uncore

Master Data Parity Error Detected (DPD)
This bit is set when DMI received a Poisoned completion from PCH.
This bit can only be set when the Parity Error Enable bit in the PCI 

Command register is set.

7

RO

1b

Uncore

Fast Back-to-Back (FB2B)
This bit is hardwired to 1. Writes to these bit positions have no 

effect. Device 0 does not physically connect to PCI_A. This bit is 

set to 1 (indicating fast back-to-back capability) so that the 

optimum setting for PCI_A is not limited by the Host.

6

RO

0h

5

RO

0b

Uncore

66 MHz Capable (MC66)
Does not apply to PCI Express. Must be hardwired to 0.

4

RO

1b

Uncore

Capability List (CLIST)
This bit is hardwired to 1 to indicate to the configuration software 

that this device/function implements a list of new capabilities. A list 

of new capabilities is accessed using register CAPPTR at 

configuration address offset 34h. Register CAPPTR contains an 

offset pointing to the start address within configuration space of 

this device where the Capability Identification register resides.

3:0

RO

0h