Intel G2120 CM8063701095801 User Manual

Datasheet, Volume 1

47

No additional power reduction actions are taken in the package C1 state. However, if 
the C1E sub-state is enabled, the processor automatically transitions to the lowest 
supported core clock frequency, followed by a reduction in voltage. 

The package enters the C1 low power state when:

• At least one core is in the C1 state.
• The other cores are in a C1 or lower power state. 

The package enters the C1E state when:

• All cores have directly requested C1E using MWAIT(C1) with a C1E sub-state hint.
• All cores are in a power state lower that C1/C1E but the package low power state is 

limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR.

• All cores have requested C1 using HLT or MWAIT(C1) and C1E auto-promotion is 

enabled in IA32_MISC_ENABLES.

No notification to the system occurs upon entry to C1/C1E.

A processor enters the package C3 low power state when: 

• At least one core is in the C3 state.
• The other cores are in a C3 or lower power state, and the processor has been 

granted permission by the platform. 

• The processor has requested the C6 state, but the platform only allowed C3.

In package C3-state, the L3 shared cache is snoopable.

A processor enters the package C6 low power state when:

• At least one core is in the C6 state.
• The other cores are in a C6 state, and the processor has been granted permission 

by the platform.

In package C6 state, all cores save their architectural state and have their core 
voltages reduced. The L3 shared cache is still powered and snoopable in this state.