Supermicro Xeon P4X-0034-2M-800 Data Sheet
Product codes
P4X-0034-2M-800
Intel® Xeon™ Processor with 800 MHz System Bus
Datasheet
21
input buffers. Legacy output THERMTRIP# uses a GTL+ output buffers. All of these
Asynchronous GTL+ signals follow the same DC requirements as GTL+ signals, however the
outputs are not driven high (during the logical 0-to-1 transition) by the processor. FERR#/PBE#,
IERR#, and IGNNE# have now been defined as AGTL+ asynchrnous signals as they include an
active p-MOS device. GTL+ asynchronous and AGTL+ asynchronous signals do not have setup or
hold time specifications in relation to BCLK[1:0]. However, all of the GTL+ asynchronous and
AGTL+ asynchronous signals are required to be asserted/deasserted for at least six BCLKs in order
for the processor to recognize them. See
Asynchronous GTL+ signals follow the same DC requirements as GTL+ signals, however the
outputs are not driven high (during the logical 0-to-1 transition) by the processor. FERR#/PBE#,
IERR#, and IGNNE# have now been defined as AGTL+ asynchrnous signals as they include an
active p-MOS device. GTL+ asynchronous and AGTL+ asynchronous signals do not have setup or
hold time specifications in relation to BCLK[1:0]. However, all of the GTL+ asynchronous and
AGTL+ asynchronous signals are required to be asserted/deasserted for at least six BCLKs in order
for the processor to recognize them. See
for the DC specifications for the asynchronous
GTL+ signal groups.
2.8
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is
recommended that the processor(s) be first in the TAP chain and followed by any other components
within the system. A translation buffer should be used to connect to the rest of the chain unless one
of the other components is capable of accepting an input of the appropriate voltage. Similar
considerations must be made for TCK, TMS, and TRST#. Two copies of each signal may be
required with each driving a different voltage level.
recommended that the processor(s) be first in the TAP chain and followed by any other components
within the system. A translation buffer should be used to connect to the rest of the chain unless one
of the other components is capable of accepting an input of the appropriate voltage. Similar
considerations must be made for TCK, TMS, and TRST#. Two copies of each signal may be
required with each driving a different voltage level.
2.9
Mixing Processors
Intel only supports and validates dual processor configurations in which both Intel® Xeon™
processor with 800 MHz system bus operate with the same front side bus frequency, core
frequency, and have the same internal cache sizes. Mixing components operating at different
internal clock frequencies is not supported and will not be validated by Intel [Note: Processors
within a system must operate at the same frequency per bits [15:8] of the IA-
32_FLEX_BRVID_SEL MSR; however this does not apply to frequency transitions initiated due
to thermal events, Demand-Based Switching (DBS) with Enhanced Intel SpeedStep® Technology
transitions, or assertion of the FORCEPR# signal (See
processor with 800 MHz system bus operate with the same front side bus frequency, core
frequency, and have the same internal cache sizes. Mixing components operating at different
internal clock frequencies is not supported and will not be validated by Intel [Note: Processors
within a system must operate at the same frequency per bits [15:8] of the IA-
32_FLEX_BRVID_SEL MSR; however this does not apply to frequency transitions initiated due
to thermal events, Demand-Based Switching (DBS) with Enhanced Intel SpeedStep® Technology
transitions, or assertion of the FORCEPR# signal (See
)]. Not all operating systems can
support dual processors with mixed frequencies. Intel does not support or validate operation of
processors with different cache sizes. Mixing processors of different steppings but the same model
(as per CPUID instruction) is supported. Please see the Intel® Xeon™ Processor with 800 MHz
System Bus Specification Update for the applicable mixed stepping table. Details regarding the
CPUID instruction are provided in the Intel® Processor Identification and the CPUID Instruction
application note.
processors with different cache sizes. Mixing processors of different steppings but the same model
(as per CPUID instruction) is supported. Please see the Intel® Xeon™ Processor with 800 MHz
System Bus Specification Update for the applicable mixed stepping table. Details regarding the
CPUID instruction are provided in the Intel® Processor Identification and the CPUID Instruction
application note.
2.10
Absolute Maximum and Minimum Ratings
specifies absolute maximum and minimum ratings. Within functional operation limits,
functionality and long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute maximum and
minimum ratings, neither functionality nor long term reliability can be expected. If a device is
returned to conditions within functional operation limits after having been subjected to conditions
outside these limits, but within the absolute maximum and minimum ratings, the device may be
functional, but with its lifetime degraded depending on exposure to conditions exceeding the
functional operation condition limits.
minimum ratings, neither functionality nor long term reliability can be expected. If a device is
returned to conditions within functional operation limits after having been subjected to conditions
outside these limits, but within the absolute maximum and minimum ratings, the device may be
functional, but with its lifetime degraded depending on exposure to conditions exceeding the
functional operation condition limits.