NEC Intel Xeon E5-2430 N8101-572F User Manual

Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families

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Datasheet Volume One

While individual threads can request low power C-states, power saving actions only 

take place once the core C-state is resolved. Core C-states are automatically resolved 

by the processor. For thread and core C-states, a transition to and from C0 is required 
before entering any other C-state.

The core C-state will be C1E if all actives cores have also resolved a core C1 state 

or higher.

The primary software interfaces for requesting low power idle states are through the 

MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E). 

However, software may make C-state requests using the legacy method of I/O reads 
from the ACPI-defined processor clock control registers, referred to as P_LVLx. This 

method of requesting C-states provides legacy support for operating systems that 

initiate C-state transitions via I/O reads.

P r o c e s s o r   P a c k a g e   S t a t e

C o r e   N   S t a t e

T h r e a d   1

T h r e a d   0

C o r e   0   S t a t e

T h r e a d   1

T h r e a d   0

C1

C1E

C7

C6

C3

C0

MWAIT(C1), HLT

C0

MWAIT(C7),

P_LVL4 I/O Read

MWAIT(C6),

P_LVL3 I/O Read

MWAIT(C3),

P_LVL2 I/O Read

MWAIT(C1), HLT 

(C1E Enabled)