NEC Intel Xeon E5-2420 N8101-571F User Manual

Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families

23

Datasheet Volume One

Refer to the following documents for additional information.

TDP

Thermal Design Power

TSOD

Thermal Sensor on DIMM

UDIMM

Unbuffered Dual In-line Module

Uncore

The portion of the processor comprising the shared cache, IMC, HA, PCU, UBox, 

and Intel QPI link interface.

Unit Interval

Signaling convention that is binary and unidirectional. In this binary signaling, 

one bit is sent for every edge of the forwarded clock, whether it be a rising edge 

or a falling edge. If a number of edges are collected at instances t

1

, t

2

, t

n

,...., t

k

 

then the UI at instance “n” is defined as: 
UI

 

n

 

= t

 

n

 

- t

 

n

 - 1

V

CC

Processor core power supply

V

SS

Processor ground

V

CCD_01, 

V

CCD_23

Variable power supply for the processor system memory interface. VCCD is the 

generic term for V

CCD_01, 

V

CCD_23.

x1

Refers to a Link or Port with one Physical Lane

x4

Refers to a Link or Port with four Physical Lanes

x8

Refers to a Link or Port with eight Physical Lanes

x16

Refers to a Link or Port with sixteen Physical Lanes

http://www.intel.com

http://www.intel.com

http://www.intel.com

http://www.intel.com

http://www.intel.com

• Volume 1: Basic Architecture
• Volume 2A: Instruction Set Reference, A-M 
• Volume 2B: Instruction Set Reference, N-Z 
• Volume 3A: System Programming Guide 
• Volume 3B: System Programming Guide