Supermicro XEON 2.8GHz P4X-0028-2M-800L User Manual

102

  Datasheet

In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#)
are allowed on the front side bus while the processor is in Sleep state. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and
STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the reset sequence.

Once in the Sleep state, the SLP# pin can be deasserted if another asynchronous front side bus
event occurs. The SLP# pin should only be asserted when the processor 

(and all logical processors

within the physical processor)

 is in the Stop-Grant state. SLP# assertions while the processors are

not in the Stop-Grant state is out of specification and may result in illegal operation.

While in AutoHALT Power Down and Stop-Grant states, the processor will process a front side bus
snoop. 

When the processor is in Sleep state, the processor will not process interrupts or snoop
transactions. 

Thermal Monitor is a feature of the processor that allows system designers to lower the cost of
thermal solutions, without compromising system integrity or reliability. By using a factory-tuned,
precision on-die temperature sensor, and a fast acting thermal control circuit (TCC), the processor,
without the aid of any additional software or hardware, can control the processors’ die temperature
within factory specifications under typical real-world operating conditions. Thermal Monitor thus
allows the processor and system thermal solutions to be designed much closer to the power
envelopes of real applications, instead of being designed to the much higher maximum processor
power envelopes.

Thermal Monitor controls the processor temperature by modulating (starting and stopping) the
internal processor core clocks. The processor clocks are modulated when the thermal control
circuit (TCC) is activated. Thermal Monitor uses two modes to activate the TCC: Automatic mode
and On-Demand mode. Automatic mode must be enabled via BIOS, which is required for the
processor to operate within specifications. Once automatic mode is enabled, the TCC will
activate only when the internal die temperature is very near the temperature limits of the processor.
When the TCC is enabled, and a high temperature situation exists (i.e. TCC is active), the clocks
will be modulated by maintaining a duty cycle within a range of 30% - 50%. Clocks will not be off
or on more than 3.0 ms when the TCC is active. Cycle times are processor speed dependent and
will decrease as processor core frequencies increase. A small amount of hysteresis has been
included to prevent rapid active/inactive transitions of the TCC when the processor temperature is
near the trip point. Once the temperature has returned to a non-critical level, and the hysteresis
timer has expired, modulation ceases and the TCC goes inactive. Processor performance will be
decreased by ~50% when the TCC is active (assuming a duty cycle that varies from 30%-50%),
however, with a properly designed and characterized thermal solution the TCC most likely will
only be activated briefly during the most power intensive applications while at maximum chassis
ambient temperature.