Supermicro XEON 2.8GHz P4X-0028-2M-800L User Manual
Product codes
P4X-0028-2M-800L
Intel® Xeon™ Processor with 512 KB L2 Cache
Datasheet
41
Figure 12. Front Side Bus Reset and Configuration Timing Waveform
Figure 13.
Power-On Reset and Configuration Timing Waveform
BLCK
RESET#
Configuration
Configuration
Safe
Valid
Valid
(A[31:3]#, BR0#,
SMI#, INIT#)
T
v
T
t
T
u
T
x
T
w
T
v
T
w
T
x
=
=
=
T13 (RESET# Pluse Width)
T45 (Reset Configuration Signals (A[14:5]#, BR0#, SMI#, INIT#) Setup Time)
T46 (Reset Configuration signals (A[14:5]#, BR0#, SMI#, INIT#) Hold Time)
(A[31:3]#, BR0#,
SMI#, INIT#)
BLCK
Ta = T37 (PWRGOOD Inactive Pluse Width)
VCC
PWRGOOD
RESET#
T
b
T
a
Tb = T36 (PWRGOOD to RESET# de-assertion time)