Intel i5-3380M AW8063801109500 User Manual
Product codes
AW8063801109500
Datasheet, Volume 1
107
Electrical Specifications
3.
The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE pins at the
socket with a 100-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-MΩ minimum
impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external
noise from the system is not coupled into the oscilloscope probe.
4.
PSx refers to the voltage regulator power state as set by the SVID protocol.
5.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. This
differs from the VID employed by the processor during a power or thermal management event (Intel
Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States).
Table 7-11. DDR3 / DDR3L / DDR3L-RS Signal Group DC Specifications (Sheet 1 of 2)
Symbol
Parameter
Min
Typ
Max
Units
Notes
1
V
IL
Input Low Voltage
—
—
SM_VREF -0.1
V
2, 4, 11
V
IH
Input High Voltage
SM_VREF +
0.1
—
—
V
3, 11
V
IL
Input Low Voltage
(SM_DRAMPWROK)
—
—
V
DDQ
*0.55 -0.1
V
10
V
IH
Input High Voltage
(SM_DRAMPWROK)
V
DDQ
*0.55
+0.1
—
—
V
10
V
OL
Output Low Voltage
—
(V
DDQ
/ 2)* (R
ON
/(R
ON
+R
TERM
))
—
6
V
OH
Output High
Voltage
—
V
DDQ
- ((V
DDQ
/ 2)*
(R
ON
/(R
ON
+R
TERM
))
—
V
4, 6
R
ON_UP(DQ)
DDR3 Data Buffer
pull-up Resistance
20
28.6
40
Ω
5
R
ON_DN(DQ)
DDR3 Data Buffer
pull-down
Resistance
20
28.6
40
Ω
5
R
ODT(DQ)
DDR3 On-die
termination
equivalent
resistance for data
signals
40
50
60
Ω
V
ODT(DC)
DDR3 On-die
termination DC
working point
(driver set to
receive mode)
0.4*V
DDQ
0.5*V
DDQ
0.6*V
DDQ
V
R
ON_UP(CK)
DDR3 Clock Buffer
pull-up Resistance
20
26
40
Ω
5, 12
R
ON_DN(CK)
DDR3 Clock Buffer
pull-down
Resistance
20
26
40
Ω
5, 12
R
ON_UP(CMD)
DDR3 Command
Buffer pull-up
Resistance
15
20
25
Ω
5, 12
R
ON_DN(CMD)
DDR3 Command
Buffer pull-down
Resistance
15
20
25
Ω
5, 12
R
ON_UP(CTL)
DDR3 Control
Buffer pull-up
Resistance
15
20
25
Ω
5, 12
R
ON_DN(CTL)
DDR3 Control
Buffer pull-down
Resistance
15
20
25
Ω
5, 12