Intel 2030M AW8063801120500 Data Sheet

Datasheet

89

HALT is a low power state entered when all the processor cores have executed the HALT 

or MWAIT instructions. When one of the processor cores executes the HALT instruction, 

that processor core is halted, however, the other processor continues normal operation. 

The processor will transition to the Normal state upon the occurrence of SMI#, INIT#, 

or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize 

itself.

The return from a System Management Interrupt (SMI) handler can be to either 

Normal Mode or the HALT Power Down state. See the Intel Architecture Software 

Developer's Manual, Volume III: System Programmer's Guide for more information.

The system can generate a STPCLK# while the processor is in the HALT powerdown 

state. When the system de-asserts the STPCLK# interrupt, the processor will return 

execution to the HALT state.

While in HALT powerdown state, the processor will process bus snoops.

Extended HALT is a low power state entered when all processor cores have executed 

the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS. 

When one of the processor cores executes the HALT instruction, that logical processor 

is halted; however, the other processor continues normal operation. The Extended 

HALT powerdown state must be enabled via the BIOS for the processor to remain 

within its specification.

The processor will automatically transition to a lower frequency and voltage operating 

point before entering the Extended HALT state. Note that the processor FSB frequency 

is not altered; only the internal core frequency is changed. When entering the low 

power state, the processor will first switch to the lower bus ratio and then transition to 

the lower VID.

While in Extended HALT state, the processor will process bus snoops.

The processor exits the Extended HALT state when a break event occurs. When the 

processor exits the Extended HALT state, it will resume operation at the lower 

frequency, transition the VID to the original value, and then change the bus ratio back 

to the original value.

The processor supports the Stop Grant and Extended Stop Grant states. The Extended 

Stop Grant state is a feature that must be configured and enabled via the BIOS. Refer 

to the following sections for details about the Stop Grant and Extended Stop Grant 

states.