Intel i3-3130M AW8063801111500 User Manual

Datasheet, Volume 1

29

The upper layer of the PCI Express architecture is the Transaction Layer. The 
Transaction Layer's primary responsibility is the assembly and disassembly of 
Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as 
read and write, as well as certain types of events. The Transaction Layer also manages 
flow control of TLPs.

The middle layer in the PCI Express stack, the Data Link Layer, serves as an 
intermediate stage between the Transaction Layer and the Physical Layer. 
Responsibilities of Data Link Layer include link management, error detection, and error 
correction.

The transmission side of the Data Link Layer accepts TLPs assembled by the 
Transaction Layer, calculates and applies data protection code and TLP sequence 
number, and submits them to Physical Layer for transmission across the Link. The 
receiving Data Link Layer is responsible for checking the integrity of received TLPs and 
for submitting them to the Transaction Layer for further processing. On detection of TLP 
error(s), this layer is responsible for requesting retransmission of TLPs until information 
is correctly received, or the Link is determined to have failed. The Data Link Layer also 
generates and consumes packets which are used for Link management functions.

The Physical Layer includes all circuitry for interface operation, including driver and 
input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), clock recovery 
circuits and impedance matching circuitry. It also includes logical functions related to 
interface initialization and maintenance. The Physical Layer exchanges data with the 
Data Link Layer in an implementation-specific format, and is responsible for converting 
this to an appropriate serialized format and transmitting it across the PCI Express Link 
at a frequency and width compatible with the remote device.