Intel i3-3130M AW8063801111500 User Manual

46

Datasheet, Volume 1

• More efficient MSR interface to access APIC registers.

— To enhance inter-processor and self directed interrupt delivery as well as the 

ability to virtualize the local APIC, the APIC register set can be accessed only 

through MSR based interfaces in the x2APIC mode. The Memory Mapped IO 

(MMIO) interface used by xAPIC is not supported in the x2APIC mode.

• The semantics for accessing APIC registers have been revised to simplify the 

programming of frequently-used APIC registers by system software. Specifically 
the software semantics for using the Interrupt Command Register (ICR) and End Of 
Interrupt (EOI) registers have been modified to allow for more efficient delivery 
and dispatching of interrupts.

The x2APIC extensions are made available to system software by enabling the local 
x2APIC unit in the “x2APIC” mode. To benefit from x2APIC capabilities, a new operating 
system and a new BIOS are both needed, with special support for the x2APIC mode.

The x2APIC architecture provides backward compatibility to the xAPIC architecture and 
forward extendibility for future Intel platform innovations.

Intel x2APIC technology may not be available on all SKUs.

For more information, refer to the Intel 64 Architecture x2APIC specification at 

http://www.intel.com/products/processor/manuals/

The processor introduces a new mechanism that provides next level of system 
protection by blocking malicious software attacks from user mode code when the 
system is running in the highest privilege level.

This technology helps to protect from virus attacks and unwanted code to harm the 
system.

For more information, please refer to the Intel

).

The processor added enhanced power-performance technology which routes interrupts 
to threads or cores based on their sleep states. For example concerning energy 
savings, it routes the interrupt to the active cores without waking the deep idle cores. 
For Performance, it routes the interrupt to the idle (C1) cores without interrupting the 
already heavily loaded cores. This enhancement is mostly beneficial for high interrupt 
scenarios like Gigabit LAN, WLAN peripherals, and so on.