Intel i3-3130M AW8063801111500 User Manual

Product codes
AW8063801111500
Page of 112
Datasheet, Volume 1
51
Power Management 
Entry and exit of the C-States at the thread and core level are shown in 
While individual threads can request low power C-states, power saving actions only 
take place once the core C-state is resolved. Core C-states are automatically resolved 
by the processor. For thread and core C-states, a transition to and from C0 is required 
before entering any other C-state.
Note:
If enabled, the core C-state will be C1E if all enabled cores have also resolved a core C1 state or higher.
Figure 4-2. Idle Power Management Breakdown of the Processor Cores
Figure 4-3. Thread and Core C-State Entry and Exit
Table 4-8.
Coordination of Thread Power States at the Core Level
Processor Core 
C-State
Thread 1
C0
C1
C3
C6
Thread 0
C0
C0
C0
C0
C0
C1
C0
C1
1
C1
1
C1
1
C3
C0
C1
1
C3
C3
C6
C0
C1
1
C3
C6