Intel i3-3130M AW8063801111500 User Manual

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Datasheet, Volume 1

A processor enters the package C3 low power state when:

• At least one core is in the C3 state
• The other cores are in a C3 or lower power state, and the processor has been 

granted permission by the platform

• The platform has not granted a request to a package C6 state but has allowed a 

package C6 state

In package C3-state, the L3 shared cache is valid.

A processor enters the package C6 low power state when:

• At least one core is in the C6 state
• The other cores are in a C6 or lower power state and the processor has been 

granted permission by the platform

In package C6 state, all cores have saved their architectural state and have had their 
core voltages reduced to zero volts. The L3 shared cache is still powered and snoopable 
in this state. The processor remains in package C6 state as long as any part of the L3 
cache is active.

The main memory is power managed during normal operation and in low-power ACPI 
Cx states.

Any System Memory (SM) interface signal that goes to a memory module connector in 
which it is not connected to any actual memory devices (such as SO-DIMM connector is 
unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM 
signals are:

• Reduced power consumption
• Reduced possible overshoot/undershoot signal quality issues seen by the processor 

I/O buffer receivers caused by reflections from potentially un-terminated 
transmission lines

When a given rank is not populated, the corresponding chip select and CKE signals are 
not driven.

At reset, all rows must be assumed to be populated, until it can be proven that they are 
not populated. This is due to the fact that when CKE is tri-stated with a SO-DIMM 
present, the SO-DIMM is not ensured to maintain data integrity.

SCKE tri-state should be enabled by BIOS where appropriate, since at reset all rows 
must be assumed to be populated.