Intel i3-3130M AW8063801111500 User Manual

Product codes
AW8063801111500
Page of 112
Datasheet, Volume 1
59
Power Management 
The target behavior is to enter self-refresh for the package C3 and C6 states as long as 
there are no memory requests to service.
4.3.2.3
Dynamic Power Down Operation
Dynamic power down of memory is employed during normal operation. Based on idle 
conditions, a given memory rank may be powered down. The IMC implements 
aggressive CKE control to dynamically put the DRAM devices in a power down state. 
The processor core controller can be configured to put the devices in active power down 
(CKE de-assertion with open pages) or precharge power down (CKE de-assertion with 
all pages closed). Precharge power down provides greater power savings but has a 
bigger performance impact, since all pages will first be closed before putting the 
devices in power down mode.
If dynamic power down is enabled, all ranks are powered up before doing a refresh 
cycle and all ranks are powered down at the end of refresh.
4.3.2.4
DRAM I/O Power Management
Unused signals should be disabled to save power and reduce electromagnetic 
interference. This includes all signals associated with an unused memory channel. 
Clocks can be controlled on a per SO-DIMM basis. Exceptions are made for per SO-
DIMM control signals such as CS#, CKE, and ODT for unpopulated SO-DIMM slots.
The I/O buffer for an unused signal should be tri-stated (output driver disabled), the 
input receiver (differential sense-amp) should be disabled, and any DLL circuitry 
related ONLY to unused signals should be disabled. The input path must be gated to 
prevent spurious results due to noise on the unused signals (typically handled 
automatically when input receiver is disabled).
4.3.3
DDR Electrical Power Gating (EPG)
The DDR I/O of the processor supports on-die Electrical Power Gating (DDR-EPG) 
during normal operation (S0 mode) while the processor is at package C3 or deeper 
power state.
During EPG, the V
CCIO
 internal voltage rail will be powered down, while V
DDQ
 and the 
un-gated V
CCIO
 will stay powered on.
The processor will transition in and out of DDR EPG mode on an as needed basis 
without any external pins or signals.
There is no change to the signals driven by the processor to the DIMMs during DDR IO 
EPG mode.
During EPG mode, all the DDR IO logic will be powered down, except for the Physical 
Control registers that are powered by the un-gated V
CCIO
 power supply.
Unlike S3 exit, at DDR EPG exit, the DDR will not go through training mode. Rather, it 
will use the previous training information retained in the physical control registers and 
will immediately resume normal operation.