Intel i3-3130M AW8063801111500 User Manual

80

Datasheet, Volume 1

The V

CCSA

 is configured by the processor output land VCCSA_VID. VCCSA_VID output 

default logic state is low for 2nd generation and 3rd generation Desktop Core 
processors, and configures V

CCSA

 to 0.925

 V.

The following are the general types of reserved (RSVD) signals and connection 
guidelines:

• RSVD – these signals should not be connected.
• RSVD_TP – these signals must be routed to a test point. Failure to route these 

signal to test points will restrict Intel’s ability to assist in platform debug.

• RSVD_NCTF – these signals are non-critical to function and may be left un-

connected.

Arbitrary connection of these signals to V

CC

, V

CCIO

, V

DDQ

, V

CCPLL

, V

CCSA, 

V

AXG,

 V

SS

, or 

to any other signal (including each other) may result in component malfunction or 
incompatibility with future processors. See 

 for a land listing of the processor 

and the location of all reserved signals.

For reliable operation, always connect unused inputs or bi-directional signals to an 
appropriate signal level. Unused active high inputs should be connected through a 
resistor to ground (V

SS

). Unused outputs maybe left unconnected; however, this may 

interfere with some Test Access Port (TAP) functions, complicate debug probing, and 
prevent boundary scan testing. A resistor must be used when tying bi-directional 
signals to power or ground. When tying any signal to power or ground, a resistor will 
also allow for system testability. For details, see 

Signals are grouped by buffer type and similar characteristics as listed in 

buffer type indicates which signaling technology and specifications apply to the signals. 
All the differential signals and selected DDR3 and Control Sideband signals have On-Die 
Termination (ODT) resistors. There are some signals that do not have ODT and need to 
be terminated on the board.