Transcend 512MB DDR2 667 DIMM 5-5-5 TS64MLQ64V6J User Manual
Product codes
TS64MLQ64V6J
T
T
T
S
S
S
6
6
6
4
4
4
M
M
M
L
L
L
Q
Q
Q
6
6
6
4
4
4
V
V
V
6
6
6
J
J
J
240PIN DDR2 667 Unbuffered DIMM
512MB With 64Mx8 CL5
Transcend Information Inc.
1
Description
The TS64MLQ64V6J is a 64M x 64bits DDR2-667
Unbuffered DIMM. The TS64MLQ64V6J consists of 8 pcs
64Mx8bits DDR2 SDRAMs in 60 ball FBGA packages
and a 2048 bits serial EEPROM on a 240-pin printed
circuit board. The TS64MLQ64V6J is a Dual In-Line
Memory Module and is intended for mounting into 240-pin
edge connector sockets.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operation frequencies,
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
Features
• RoHS compliant products
• JEDEC standard 1.8V ± 0.1V Power supply
• VDDQ=1.8V ± 0.1V
• Max clock Freq: 333MHZ; 667Mb/S/Pin.
• Posted CAS
• Programmable CAS Latency: 3,4,5
• Programmable Additive Latency :0, 1,2,3 and 4
• Write Latency (WL) = Read Latency (RL)-1
• Burst Length: 4,8(Interleave/nibble sequential)
• Programmable sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended
• JEDEC standard 1.8V ± 0.1V Power supply
• VDDQ=1.8V ± 0.1V
• Max clock Freq: 333MHZ; 667Mb/S/Pin.
• Posted CAS
• Programmable CAS Latency: 3,4,5
• Programmable Additive Latency :0, 1,2,3 and 4
• Write Latency (WL) = Read Latency (RL)-1
• Burst Length: 4,8(Interleave/nibble sequential)
• Programmable sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended
data-strobe is an optional feature)
• Off-Chip Driver (OCD) Impedance Adjustment
• MRS cycle with address key programs.
• On Die Termination
• Serial presence detect with EEPROM
• MRS cycle with address key programs.
• On Die Termination
• Serial presence detect with EEPROM
Placement
L
A
C
H
J
I
K
B
G
D
E
F
M
PCB: 09-2285