Elpida 1GB DDR3 1600MHz EDJ1116EJBG User Manual

Preliminary Data Sheet E1949E11 (Ver. 1.1)

3

×8 configuration)

/xxx indicates active low signal.

Notes: 1.

Not internally connected with die.

2.

Don't connect. Internally connected.

3.

Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.

A0 to A13*

Address inputs

A10(AP): Auto precharge
A12(/BC): Burst chop

/RESET*

Active low asynchronous reset

BA0 to BA2*

Bank select

VDD

Supply voltage for internal circuit

DQ0 to DQ7

Data input/output

VSS

Ground for internal circuit

DQS, /DQS

Differential data strobe

VDDQ

Supply voltage for DQ circuit

TDQS, /TDQS

Termination data strobe

VSSQ

Ground for DQ circuit

/CS*

Chip select

VREFDQ

Reference voltage for DQ

/RAS, /CAS, /WE*

Command input

VREFCA

Reference voltage for CA

CKE*

Clock enable

ZQ

Reference pin for ZQ calibration

CK, /CK

Differential clock input

NC*

No connection

DM

Write data mask

NU*

Not usable

ODT*

ODT control

VSS

VDD

1

VDDQ

VSS

VSS

2

VSSQ

DQ0

VSS

DQ2

DQ6

VSSQ

VDDQ

VREFDQ

VSS

VDD

/CS

BA0

A7

/RESET

NC

NC

VDD

3

NC

DQS

/DQS

DQ4

/RAS

/CAS

/WE

BA2

A9

A13

7

NU/(/TDQS)

DM/TDQS

DQ1

VDD

DQ7

CK

/CK

A10(AP)

NC

A11

NC

8

VSS

VSSQ VDDQ

VSSQ

DQ3

VSS

DQ5

VSS

VDD

ZQ

VREFCA

A6

A8

CKE

VSS

VSS

9

VDD

VSSQ

VDDQ

NC

VDD

(Top view)

78-ball FBGA 

ODT

NC

A

B

C

D

E

F

G

H

J

A3

VDD

A0

A12(/BC) BA1

VDD

A5

VSS

A2

A1

A4

VSS

K

L

M

N