Intel i3-3245 BX80637I33245 User Manual

Intel

Product codes

BX80637I33245

6

Datasheet, Volume 1

Signal Groups................................................................................................... 80

Test Access Port (TAP) Connection ...................................................................... 82

Storage Conditions Specifications........................................................................ 83

7.10 DC Specifications .............................................................................................. 84

7.10.1 Voltage and Current Specifications ........................................................... 84

7.11 Platform Environmental Control Interface (PECI) DC Specifications .......................... 90

7.11.1 PECI Bus Architecture............................................................................. 90
7.11.2 DC Characteristics ................................................................................. 91
7.11.3 Input Device Hysteresis .......................................................................... 91

Processor Land and Signal Information................................................................... 93
8.1

Processor Land Assignments .............................................................................. 93

DDR Data Swizzling................................................................................................109

Figures

Desktop Processor Platform..................................................................................... 10

Desktop Processor Compatibility Diagram ................................................................. 18

®

Flex Memory Technology Operation ................................................................ 26

PCI Express* Layering Diagram ............................................................................... 28

Packet Flow Through the Layers............................................................................... 29

PCI Express* Related Register Structures in the Processor .......................................... 30

PCI Express* Typical Operation 16 Lanes Mapping ..................................................... 31

Processor Graphics Controller Unit Block Diagram ...................................................... 33

Processor Display Block Diagram ............................................................................. 36

Processor Power States .......................................................................................... 47

Idle Power Management Breakdown of the Processor Cores ......................................... 51

Thread and Core C-State Entry and Exit.................................................................... 51

Package C-State Entry and Exit ............................................................................... 55

Example for PECI Host-Clients Connection................................................................. 90

Input Device Hysteresis .......................................................................................... 91

LGA Socket Land Map............................................................................................. 94

Tables

Desktop 3rd Generation Intel

Core™ Processor Family, Desktop Intel

Processor Family, and Desktop Intel

Processor Family SKUs .......... 16

Terminology.......................................................................................................... 19

Related Documents ................................................................................................ 22

Processor DIMM Support Summary by Product........................................................... 23

Supported UDIMM Module Configurations.................................................................. 24

Supported SO-DIMM Module Configurations (AIO Only)............................................... 24

System Memory Timing Support .............................................................................. 25

Reference Clock..................................................................................................... 38

System States....................................................................................................... 48

Processor Core / Package State Support ................................................................... 48

Integrated Memory Controller States........................................................................ 48

PCI Express* Link States ........................................................................................ 49

Direct Media Interface (DMI) States ......................................................................... 49

Processor Graphics Controller States ........................................................................ 49

G, S, and C State Combinations............................................................................... 49

Coordination of Thread Power States at the Core Level ............................................... 51

P_LVLx to MWAIT Conversion .................................................................................. 52

4-10 Coordination of Core Power States at the Package Level.............................................. 54
6-1

Signal Description Buffer Types ............................................................................... 65