Intermec 073290-001 User Manual

 

CPU JTAG

TM

S

TDI TD

O

TC

K

G

N

D

3.3

V

5

1

10

6

15

11

FPGA JTAG

TM

S

TDI TD

O

TC

K

G

N

D

3.3

V

RESET

1

2

19

20

G

N

D

G

N

D

G

N

D

G

N

D

G

N

D

G

N

D

N

C

CP

U

 JT

AG

N

C

N

C

RS

T

TD

O NC

TC

K

TM

S

TD

I

M

R*

3.3

V

G

N

D

G

N

D

G

N

D

I2C

SD

A

SC

K

G

N

D

TARGET

SYSTEM

FLEX

PIC PROGRAMMER

To P1 on 
target system

 

J33, J34 and J35 are 3 high-density 40-pin SMT board-to-board 
connectors providing debug board access to the CK30 system bus and 
control signals. These connectors are not installed on production boards, 
and so are not intended as a field debug facility, but could be soldered 
onto a production board to help diagnose a field problem as a last resort. 

The signal set brought out through these connectors includes: 

•  SA_MD31:0 (data bus) 

•  SA_MA25:0 (addr bus) 

•  Control signals RD/WR*, WE*, OE*, PWE*, RESET_IN*, DQM3:0, 

RDY 

•  SCAN_DREQ, PCI_IRQ, SA_BREQ, SA_BGNT 

•  SDRAM control signals SDCAS*, SDRAS*, SDCS0*, SDCKE 

•  Clocks SDCLK, FPGA_CLK 

•  Chip selects FPGA_CS*, FLASH_CS*, PCI/HCR_CS*