Intermec 073290-001 User Manual

Page of 113
Chapter 4 — Theory of Operation 
System Architecture 
The CK30 platform is a 32-bit 3.3V system, with the processor and FPGA 
cores running at 1.3V and 2.5V, respectively. The design is contained on a 
single main PCB, except for the following modules: 
•  The keypad is a separate, replaceable module that attaches to the 
exterior of the product, connected to the main PCB through a flex 
cable. 
•  The LCD and drivers are contained within a separate display module, 
connected to the main PCB through a flex cable. 
•  The two speakers are mounted on a small PCB connected to the main 
PCB through a wired cable. 
•  Radio and Ethernet options are implemented with Mini PCI Type 3A 
cards. 
MA(25:0)   MD(31:0)   Mem Control Signals
FLASH
Keypad
Matrix
JTAG
Port
Power enables
Module enables
SDRAM
232 buf
LCD
Backlight
Driver
Bias
Suppl y
HCR
Regs
FPGA
Scanner
I/F
Mini-PCI
Host
Bridge
Scanner
Conn
Scan
Engine
Mini-PCI
Slot
Mini-PCI
Radio
or 
Ethernet
GPIO
Keypad
Conn
User
LEDs
SD Slot
Dock
Conn
Touch
Panel
Conn
Spkr
Conn
Touch
Panel I/F
3.3V
Suppl y
5V
Supply
Supercap
Suppl y
Supercap
Charger
Debug Board
with:
AC97
Codec
Audio
Driver
Bluetooth
Module
Main
Battery
Conn
Supercap
System 3.3V
System 5V
1.3V CPU
Core Supply
2.5V FPGA
Core Supply
MIC
Conn
I2C I/F
ST UART
Power
Supply
Controller
IO Key
Low Batt
Detect
Speakers
LCD Conn
Battery,
Supercap,
Temperature
Monitoring
Low 3.3V
POR
MCLR
Other signals
of interest
32kHz
OSC
3.68MHz
OSC
MMC I/F
Memory
Controller
I/F
GPIO
FF UART
Power
Management
Pins
BT UART
PWM1
AC97 I/F
SPI I/F
LCD
I/F
JTAG Pins
PXA255
Processor
Dashed indicates optional feature
(Color or Monochrome)
Battery
Status LED
Debug
Conns
- Ethernet controller
- Debug LEDs
- Logic Analyzer
   connectors
PWM0
Enables 
from HCR
Ethernet
Scan I/F
USB I/F
Reset
Resume
Logic
GPIO_0,
GPIO_1
I/O
Optional
10-pin
Tethered
Scan Port
 
 
CK30 High-Level Block Diagram 
40 
CK30 Handheld Computer Service Manual