Intermec 073290-001 User Manual

The loader then writes byte values to the FPGA, with write strobe PWE* 
serving as the CCLK download clock. The FPGA IO is nominally Hi-Z 
during download. When the download is complete, the FPGA enables its 
outputs. When its internal DLLs have locked, it raises its DONE output 
(alternate function of signal SCAN_IRQ*) to signal the download was 
successful. Software then initializes the FPGA internal register settings. See 
Xilinx datasheets and app notes for details of the parallel slave download 
scheme. 

After download, signals SCAN_DREQ and SCAN_IRQ* are no longer 
used by the FPGA as download status indications and take on their 
programmed functions of scanner DMA request and scanner interrupt 
line. 

Because of the fairly high operating and standby currents of the FPGA, it 
must be powered off during Suspend. Since it will lose its configuration 
when power is removed, its image must be re-downloaded on every 
resume. This also limits its use to functions that are needed only at run 
time. 

The FPGA uses separate core and IO supplies. 3.3V is switched through 
FET Q1 to the FPGA IO supply pins. A separate switchable 2.5V supply 
(U43) is provided for the FPGA core voltage. 

The 2.5V supply is enabled and disabled under software control via the 
FPGA_PWR_EN* signal, inverted through U51. A section of operational 
amplifiers U41 functions as a slow turn-on control for U43. This prevents 
a crippling inrush current surge that would otherwise result if the core 
supply were brought rapidly to 2.5V. 

The FPGA 3.3V IO ring supply is controlled separately through the Power 
Supply Controller (U38) so that it can be sequenced off well after (about 
10ms) the FPGA core voltage has been turned off and the PXA255 has 
suspended. This ensures the FPGA IO remains stable while the core is 
being switched off. 

•  On PWR_EN high (CPU waking or booting), the PSC enables the 

FPGA IO ring power supply. 

•  On PWR_EN low (CPU suspending), the PSC waits 10ms and then 

disables the FPGA IO ring power supply. This ensures that the FPGA 
core supply (controlled by the CPU) goes down first, avoiding a failure 
mode in which FPGA IO pins pulse low when its IO ring and core 
supplies go down simultaneously. 

•  On cold boot, the PSC holds the FPGA IO supply off for 100ms before 

releasing system reset and enabling the FPGA supply. This ensures that 
the FPGA IO initializes correctly to a high impedance state on cold 
boot, avoiding another failure mode that can occur if the FPGA latches 
in an erroneous state that can inhibit the PXA255 from booting.