Intermec 073290-001 User Manual
Chapter 4 — Theory of Operation
Suspend Events
Source
Conditions
I key (Suspend/Resume)
None
OS auto-suspend timer
None
Application-program-initiated suspend
None
Suspend through Reader Command
None
Hardware critically low battery threshold
(includes battery removal)
(includes battery removal)
Instantaneous battery level falls below
U36 hardware critical-battery threshold.
For help, see the “Low-Battery
Thresholds” table on page 61.
U36 hardware critical-battery threshold.
For help, see the “Low-Battery
Thresholds” table on page 61.
Display
LCD Panel
The CK30AA and CK30BA use a 160 x 160 transflective monochrome
display with a gray-scale depth of 4 bits per pixel.
display with a gray-scale depth of 4 bits per pixel.
The CK30CA uses a 160 x 160 transflective, passive color display with a
color depth of 16 bits per pixel.
color depth of 16 bits per pixel.
LCD Controller
The PXA255 internal LCD controller used to drive the display through an
8-bit LCD interface. The PXA255 LCD controller has no dedicated frame
buffer, but instead uses a Unified Memory Architecture: the display refresh
data is stored in system SDRAM and is direct memory accessed to the
LCD controller. The DMA controller is dedicated to the LCD controller
and runs independently of the main PXA255 DMA controller.
8-bit LCD interface. The PXA255 LCD controller has no dedicated frame
buffer, but instead uses a Unified Memory Architecture: the display refresh
data is stored in system SDRAM and is direct memory accessed to the
LCD controller. The DMA controller is dedicated to the LCD controller
and runs independently of the main PXA255 DMA controller.
Bias Supply
Color: +16.6 to +19.3 VDC.
Mono: + 18.5 to +23.7 VDC (variable for contrast adjust).
Display Contrast Control
Display contrast is controlled through PXA255 PWM output PWM0
(signal CONTRAST). Software adjusts the duty cycle of the pulses on this
output. The pulse stream is filtered through R213, C160, R214, and
C159 to produce a DC value at the feedback pin of boost switcher U37,
setting the output voltage.
(signal CONTRAST). Software adjusts the duty cycle of the pulses on this
output. The pulse stream is filtered through R213, C160, R214, and
C159 to produce a DC value at the feedback pin of boost switcher U37,
setting the output voltage.
Because the optimal contrast setting varies from display to display, the
default setting is dialed at Final Test and saved in system flash. You can
then adjust the contrast up or down from this midpoint, with the revised
setting saved in the system registry so that it is reapplied after warm or cold
default setting is dialed at Final Test and saved in system flash. You can
then adjust the contrast up or down from this midpoint, with the revised
setting saved in the system registry so that it is reapplied after warm or cold
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CK30 Handheld Computer Service Manual