Intermec 073290-001 User Manual

Horizontal (DBP_HSYNC) and vertical (SOS_VSYNC) sync pulses from 
the scanner mark the start of lines and frames, respectively. 

The 8-bit pixel data is collected in a 32-deep FIFO, which in turn feeds a 
16-deep 32-bit-wide DMA buffer. When the DMA buffer is half full, the 
FPGA asserts SCAN_DREQ to the PXA255 to request a DMA transfer, 
and 8 32-bit words are direct memory accessed into a cached area of 
system SDRAM for decoding. 

Although the imager resolution is 640x480, it actually sends 525 lines of 
852 bytes per line. Counters in the FPGA track when the first valid line 
and column bytes arrive, so only valid data is sent to the FIFO. 

The “Blur Detect, Exposure Sense” block in the block diagram represents 
2 special logic functions in the FPGA:   

•  Averaging logic: This logic calculates the average pixel value over 2 

rectangular regions of the image – one 256x256, and one 256x64. The 
average pixel values are read by software through registers in the FPGA, 
and used to adjust the scanner illumination. If the optimum exposure 
can’t be achieved through illumination, software then adjusts the 
imager’s integration time via I2C commands. 

•  Horizontal Focus Factor: This logic performs a rolling sum of squares 

of deltas between adjacent pixels in a line to determine if the image is 
blurred from movement. This result is read by software through a 
register in the FPGA to decide if the captured image is too out of focus 
to attempt a decode. 

See 630063, Andromeda Imager Host Interconnect Architecture Spec, for 
more detail on this scanner interface. 

Internal scanners using the MDS interface (currently only the EV10) are 
handled through an SPI interface in the FPGA. This is a future addition 
that is not yet covered in this document. 

Internal or tethered scanners with built-in decode are typically supported 
using an asynchronous serial interface (RSTTL, or RS-232 at TTL signal 
level).