Hynix 8GB DDR3 PC3-10600 HMT41GU7MFR8C-H9 User Manual

V

IX

(CK)

Differential Input Cross Point Voltage 

relative to VDD/2 for CK, CK

-150

150

mV

2

-175

175

mV

1

V

IX

(DQS)

Differential Input Cross Point Voltage 

relative to VDD/2 for DQS, DQS

-150

150

mV

2

Notes:
1. Extended range for V

IX

 is only allowed for clock and if single-ended clock input signals CK and CK are 

monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential 

slew rate of CK - CK is larger than 3 V/ns.



2. Refer to the table "Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU" on page 22 

for VSEL and VSEH standard values.

See 7.5 “Address / Command Setup, Hold and Derating” in “DDR3 Device Operation” for single-ended slew 

rate definitions for address and command signals.


See 7.6 “Data Setup, Hold and Slew Rate Derating”  in “DDR3 Device Operation” for single-ended slew rate 

definition for data signals.