Hynix 8GB DDR3 PC3-12800 HMT31GR7CFR4C-PB User Manual

1. Used to define a differential signal slew-rate.
2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL 

(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level 
applies also here.

3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU 

need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 43.

note : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling 

input differential signal shall become equal to or less than VIL(ac) level.

VIHdiff

Differential input high

+ 0.180

Note 3

V

1

VILdiff

Differential input logic low

Note 3

- 0.180

V

1

VIHdiff (ac)

Differential input high ac

2 x (VIH (ac) - Vref)

Note 3

V

2

VILdiff (ac)

Differential input low ac

Note 3

2 x (VIL (ac) - Vref)

V

2

> 4.0

75

-

175

-

214

-

134

-

4.0

57

-

170

-

214

-

134

-

3.0

50

-

167

-

191

-

112

-

2.0

38

-

119

146

67

1.8

34

-

102

-

131

-

52

-

1.6

29

-

81

-

113

-

33

-

1.4

22

-

54

-

88

-

9

-

1.2

note

-

19

-

56

-

note

-

1.0

note

-

note

-

11

-

note

-

< 1.0

note

-

note

-

note

-

note

-