Hynix 8GB DDR3 PC3-12800 HMT31GR7CFR4C-PB User Manual

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and 

strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the 

requirements in table below. The differential input cross point voltage VIX is measured from the actual 

cross point of true and complement signals to the midlevel between of VDD and VSS

Notes:
1. The relation between Vix Min/Max and VSEL/VSEH should satisfy following.



(VDD/2) + Vix (Min) - VSEL 



 25mV 



VSEH - ((VDD/2) + Vix (Max)) 



 25mV 

V

IX

Differential Input Cross Point Voltage 

relative to VDD/2 for CK, CK

-150

150

mV

1

V

IX

Differential Input Cross Point Voltage 

relative to VDD/2 for DQS, DQS

-150

150

mV

1