Intel E3-1240 v3 BX80646E31240V3 User Manual

A small amount of hysteresis has been included to prevent rapid active/inactive

transitions of the TCC when the processor temperature is near the TCC activation

temperature. Once the temperature has dropped below the trip temperature and the

hysteresis timer has expired, the operating frequency and voltage transition back to

the normal system operating point using the intermediate VID/frequency points.

Transition of the VID code will occur first, to insure proper operation as the frequency

is increased.

Clock modulation is a second method of thermal control available to the processor.

Clock modulation is performed by rapidly turning the clocks off and on at a duty cycle

that should reduce power dissipation by about 50% (typically a 30–50% duty cycle).

Clocks often will not be off for more than 32 microseconds when the TCC is active.

Cycle times are independent of processor frequency. The duty cycle for the TCC, when

activated by the Thermal Monitor, is factory configured and cannot be modified.

It is possible for software to initiate clock modulation with configurable duty cycles.

A small amount of hysteresis has been included to prevent rapid active/inactive

transitions of the TCC when the processor temperature is near its maximum operating

temperature. Once the temperature has dropped below the maximum operating

temperature and the hysteresis timer has expired, the TCC goes inactive and clock

modulation ceases.

When the TCC is activated, the processor will sequentially step down the ratio

multipliers and VIDs in an attempt to reduce the silicon temperature. If the

temperature continues to increase and exceeds the TCC activation temperature by

approximately 5 °C before the lowest ratio/VID combination has been reached, the

processor will immediately transition to the combined TM1/TM2 condition. The

processor remains in this state until the temperature has dropped below the TCC

activation point. Once below the TCC activation temperature, TM1 will be discontinued

and TM2 will be exited by stepping up to the appropriate ratio/VID state.

If TM2 is unable to reduce the processor temperature, then TM1 will be also be

activated. TM1 and TM2 will then work together to reduce power dissipation and

temperature. It is expected that only a catastrophic thermal solution failure would

create a situation where both TM1 and TM2 are active.

If TM1 and TM2 have both been active for greater than 20 ms and the processor

temperature has not dropped below the TCC activation point, the Critical Temperature

Flag in the IA32_THERM_STATUS MSR will be set. This flag is an indicator of a

catastrophic thermal solution failure and that the processor cannot reduce its

temperature. Unless immediate action is taken to resolve the failure, the processor

will probably reach the Thermtrip temperature (see 

 on page 82)

within a short time. To prevent possible permanent silicon damage, Intel recommends

removing power from the processor within ½ second of the Critical Temperature Flag

being set.

Intel

®

 Xeon

®

 Processor E3-1200 v3 Product Family

June 2013

Datasheet – Volume 1 of 2

Order No.: 328907-001

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