Intermec 073289-001 User Manual

Connector J17 is modified with a retainer clip (to hold the card in place 
during a drop) and a “debounce plate” assembly that increases the contact 
force on the card to minimize contact bounce during drop. Unfortunately, 
the added contact force tends to defeat the slot’s normal push-push card 
latching mechanism, making the card difficult to remove. 

CK30 audio tones are simple square wave tones generated by one of the 
PXA255’s 2 Pulse Width Modulators. Tone duration is software-
controlled, based on OS timer ticks. 

The 3.3V PWM output (signal BEEP) is first divided down through a 
crude volume control formed by resistors R126 through R129. The 3 
“base legs” of the resistive divider are driven by open-drain outputs of 
FPGA U8 so that the divide ratio can be set to 1 of 8 levels under software 
control. The resistor values are chosen so that software could select at least 
4 levels (out of the 8 possible combinations) that roughly approximate a 
logarithmic volume scale. 

The scaled square wave is AC coupled to audio amplifier U19, which 
drives 2 side-emitting 8-ohm electromagnetic transducers, wired in parallel 
and mounted on a small PCB embedded in the display shock mount. U19 
is a push-pull amplifier powered from the 5V rail to maximize the peak-
peak square wave across the speakers. At max volume the P-P output is 
about 7.3V (limited by the amplifier’s 3W drive limit). 

Software enables U19 through HCR register U16 output AUDIO_EN 
driving FET Q14, and shuts it off during Suspend for power savings (U19 
draws about 7mA while idle). On Suspend AUDIO_EN must be turned 
before the 5V supply decays to avoid any undesirable sound effects. 

AUDIO_EN is automatically disabled in a critical battery situation by the 
“Type 1” interlock mechanism described in “Device Power Control” on 
page 58. In this situation, system software also immediately writes a 0 to 
the AUDIO_EN bit in HCR register U16. This prevents the system from 
oscillating if audio activity contributed to the low-battery threshold being 
crossed: with the audio load suddenly removed by AUDIO_EN going low, 
the battery voltage can rapidly recover enough that HCR_DISABLE is de-
asserted. If the AUDIO_EN bit on U16 were left high, that would reapply 
the audio load, causing the battery voltage to crash again. 

C104 provides “pop” protection when U19 is enabled, but also delays the 
audio amplifier bias stabilizing, so there is a delay of about 150ms to 
200ms before the amplifier is usable. This delay is why the amplifier 
cannot be left disabled while idle, and enabled only when needed. 

The BEEP signal is also routed to the FPGA, for 2 purposes: 

•  When a tethered undecoded scanner is being used, the FPGA is 

configured to route the BEEP signal through to the scanner on the 
IMAGER_PIXCLK line to scanner connector J3.