Intermec 073289-001 User Manual
Chapter 4 — Theory of Operation
FPGA_CLK 49.77MHz.
Enabled
immediately before FPGA
download. FPGA_CLK serves both the scanner
interface and Mini PCI bridge resident in the FPGA.
interface and Mini PCI bridge resident in the FPGA.
Audio
Codec sampling in computers equipped with audio is
based on the audio codec local 24.576MHz oscillator.
based on the audio codec local 24.576MHz oscillator.
Memory
RAM
U6 and U7 constitute the system RAM: 32MBs for the CK30AA and
CK30BA, and 64MBs for the CK30CA. The SDRAM is interfaced at
3.3V bus levels through the PXA255 memory controller, at 99.5MHz with
CAS latency of 2. The processor’s “Normal Mode” addressing scheme is
used.
CK30BA, and 64MBs for the CK30CA. The SDRAM is interfaced at
3.3V bus levels through the PXA255 memory controller, at 99.5MHz with
CAS latency of 2. The processor’s “Normal Mode” addressing scheme is
used.
SDRAM size is checked by the bootloader at boot time to configure the
memory controller for different SDRAM BankxRowxColumn geometries.
The same CAS-before-RAS refresh period of 8µs is used for both 128Mbit
and 256Mbit SDRAM densities.
memory controller for different SDRAM BankxRowxColumn geometries.
The same CAS-before-RAS refresh period of 8µs is used for both 128Mbit
and 256Mbit SDRAM densities.
In the current CK30 32MB and 64MB configurations, the SDRAM
occupies partition 0 of the processor’s SDRAM space. Provision is made
through not-installed AND gate U3 to support 128MB SDRAM using
512MB chips. In this case, the SDRAM occupies partitions 0 and 1.
occupies partition 0 of the processor’s SDRAM space. Provision is made
through not-installed AND gate U3 to support 128MB SDRAM using
512MB chips. In this case, the SDRAM occupies partitions 0 and 1.
FPGA U8 is an alternate bus master that can request the system bus and
take over control of the SDRAM. When U8 is in control, it runs the
SDRAM at 49.77MHz. For more information, see “SDRAM Controller”
on page 71.
take over control of the SDRAM. When U8 is in control, it runs the
SDRAM at 49.77MHz. For more information, see “SDRAM Controller”
on page 71.
Flash
U4 and U5 constitute the system XIP flash: 32MB for the CK30AA and
CK30BA, and 64MB for the CK30CA. Intel K3C synchronous
Strataflash is used for the 64MB configuration; the 32MB configuration
may be either J3A asynchronous or K3C synchronous Strataflash.
CK30BA, and 64MB for the CK30CA. Intel K3C synchronous
Strataflash is used for the 64MB configuration; the 32MB configuration
may be either J3A asynchronous or K3C synchronous Strataflash.
The system flash boots in asynchronous mode. The boot code reads the
flash ID and switches the flash to synchronous mode if K3C flash is
detected. Otherwise, flash is handled as asynchronous page-mode flash.
flash ID and switches the flash to synchronous mode if K3C flash is
detected. Otherwise, flash is handled as asynchronous page-mode flash.
The flash is protected against corruption through three mechanisms:
• A software-controlled block is locking within the parts themselves.
• PXA255 GPIO11 (FLASH_PROT*) must be set high by software to
allow writes.
• PXA255 output RESET_OUT* holds the flash in a low-power write-
protected state during Suspend.
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CK30 Handheld Computer Service Manual