Intermec 073292-001 User Manual

ADDR DECODE,

RD/WR CTL

PCI

IRQ CTL

SD31..0

SA25..0

SCAN_IRQ

AD31..0

HCR_WR2*
HCR_WR5*

SDBUF_D7..0

SCAN_DREQ

Host CPU

I/F

Scanner

I/F

Mini-PCI Slot

GPIO

LogiCore

PCI Core

PAR

PERR#

SERR#

FRAME#

IRDY#

TRDY#

STOP#

DEVSEL#

RST#

PCI_CLK

REQ#, GNT#

C/BE#3..0

BUS

ARBITER

Initiator

Logic

RD FIFO

DQM3..0

nOE

nPWE

RDY

RD/WR

FPGA_CS

DBP_HSYNC

SOS_VSYNC

ILLUM_LASEN_RTS

SCAN_LED

SCAN_LED_LOW

TETH_DBP, SOS

TETH_PRESENT

WR FIFO

Target

Logic

RD FIFO

WR FIFO

SDRAM

Controller

USER_LED<2:1>

SCAN_TRIG*

Local

CPU

I/F

Logic

PCI

CTL

REGs

INTA#

INTB#

KEY_RET<7:0>

PCI_IRQ

BREQ, BGNT

PCI Bridge

Host I/F
Wrapper

nWE

SPEED_RANGE_GDRD

SCAN_FLASH_EN

DOCK_TRIG*

VOL<2:0>

ACT#, PME#

SDCS0

SDCAS

SDRAS

SDCLK

DLL

DLL

(/2)

FPGA_CLK

CLK_OUT

CLK

PCLK

IMAGER_PIXCLK

BATT_FAULT_IRQ

CLKRUN#

IDSEL

PCI/HCR_CS

IMAGE

CAPTURE

STATE

MACHINE

DMA

BUFFER

CTL

REGs

FIFO

DBP

COUNT

LOGIC

GPIO

IRQ

CTL

Kypd

Scanner I/F

IO MUX LOGIC

BLUR 

DETECT,

EXPOSURE

SENSE

Bus I/F

 

The FPGA is SRAM-based and must be downloaded at boot time and on 
resume. Its image is stored in system flash and downloaded from the 
PXA255 by a download driver using the FPGA parallel slave mode on data 
lines SA_MD7:0. This process clearly must precede loading of any drivers 
that expect to use the FPGA.  

Software initiates the download by pulsing the FPGA_PGM* signal low to 
clear the FPGA configuration space, waiting for its INIT status to go high 
(alternate function of signal SCAN_DREQ), and starting the 
FPGA_CLK.