Intel E3-1280 v3 CM8064601467001 User Manual

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5 GT/s point-to-point DMI interface to PCH is supported.

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Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of

500 MB/s given the 8b/10b encoding used to transmit data across this interface.

Does not account for packet overhead and link maintenance.

•

Maximum theoretical bandwidth on interface of 2 GB/s in each direction

simultaneously, for an aggregate of 4 GB/s when DMI x4.

•

Shares 100-MHz PCI Express* reference clock.

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64-bit downstream address format, but the processor never generates an address

above 64 GB (Bits 63:36 will always be zeros).

•

64-bit upstream address format, but the processor responds to upstream read

transactions to addresses above 64 GB (addresses where any of Bits 63:36 are

nonzero) with an Unsupported Request response. Upstream write transactions to

addresses above 64 GB will be dropped.

•

Supports the following traffic types to or from the PCH:
— DMI -> DRAM
— DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs

only)

— Processor core -> DMI

•

APIC and MSI interrupt messaging support:
— Message Signaled Interrupt (MSI and MSI-X) messages

•

Downstream SMI, SCI and SERR error indication.

•

Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port

DMA, floppy drive, and LPC bus masters.

•

DC coupling – no capacitors between the processor and the PCH.

•

Polarity inversion.

•

PCH end-to-end lane reversal across the link.

•

Supports Half Swing “low-power/low-voltage”.

DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or

GPE. Any DMI related SERR activity is associated with Device 0.

The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to

data link down, after the link was up, then the DMI link hangs the system by not

allowing the link to retrain to prevent data corruption. This link behavior is controlled

by the PCH.

Downstream transactions that had been successfully transmitted across the link prior

to the link going down may be processed as normal. No completions from

downstream, non-posted transactions are returned upstream over the DMI link after a

link down event.

Intel

®

 Xeon

®

 Processor E3-1200 v3 Product Family

Datasheet – Volume 1 of 2

June 2013

26

Order No.: 328907-001