Intel E3-1280 v3 CM8064601467001 User Manual

R

ON_DN(CTL)

DDR3/DDR3L Control

Buffer pull-down

Resistance

19

25

31

Ω

5, 11,

13

R

ON_UP(RST)

DDR3/DDR3L Reset

Buffer pull-up

Resistance

40

80

130

Ω

—

R

ON_DN(RST)

DDR3/DDR3L Reset

Buffer pull-up

Resistance

40

80

130

Ω

—

I

LI

Input Leakage Current

(DQ, CK)
0 V
0.2*V

DDQ

0.8*V

DDQ

—

—

0.7

mA

—

I

LI

Input Leakage Current

(CMD, CTL)
0V
0.2*V

DDQ

0.8*V

DDQ

—

—

1.0

mA

—

SM_RCOMP0

Command COMP

Resistance

99

100

101

Ω

8

SM_RCOMP1

Data COMP Resistance

74.25

75

75.75

Ω

8

SM_RCOMP2

ODT COMP Resistance

99

100

101

Ω

8

Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. V

IL

 is defined as the maximum voltage level at a receiving agent that will be interpreted as a

logical low value.

3. V

IH

 is defined as the minimum voltage level at a receiving agent that will be interpreted as a

logical high value.

4. V

IH

 and V

OH

 may experience excursions above V

DDQ

. However, input signal drivers must comply

with the signal quality specifications.

5. This is the pull up/down driver resistance.
6. R

TERM

 is the termination on the DIMM and in not controlled by the processor.

7. The minimum and maximum values for these signals are programmable by BIOS to one of the

two sets.

8. SM_RCOMPx resistance must be provided on the system board with 1% resistors. SM_RCOMPx

resistors are to V

SS

. DDR3/DDR3L values are pre-silicon estimations and are subject to change.

9. SM_DRAMPWROK rise and fall time must be < 50 ns measured between V

DDQ

 *0.15 and V

DDQ

*0.47.

10.SM_VREF is defined as V

DDQ

/2

11.Maximum-minimum range is correct but center point is subject to change during MRC boot

training.

12.Processor may be damaged if V

IH

 exceeds the maximum voltage for extended periods.

13.The MRC during boot training might optimize R

ON

 outside the range specified.

V

IL

HPD Input Low Voltage

—

—

0.8

V

V

IH

HPD Input High Voltage

2.25

—

3.6

V

Vaux(Tx)

Aux peak-to-peak voltage at transmitting

device

0.39

—

1.38

V

Vaux(Rx)

Aux peak-to-peak voltage at receiving

device

0.32

—

1.36

V

Intel

®

 Xeon

®

 Processor E3-1200 v3 Product Family

June 2013

Datasheet – Volume 1 of 2

Order No.: 328907-001

97