Intel 1005M AW8063801121200 User Manual

88

Datasheet, Volume 1

SM_RCOMP[2:0]

System Memory Impedance Compensation:  I/O

A

SM_VREF

DDR3/DDR3L/DDR3L-RS Reference Voltage: This signal is 

used as a reference voltage to the DDR3/DDR3L/DDR3L-RS 

controller.

I

A

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

Memory Channel A/B DIMM DQ Voltage Reference: These 

output pins are connected to the DIMMs, and are programmed to 

have a reference voltage with optimized margin.
The nominal source impedance for these pins is 150
The step size is 7.7 mV for DDR3 (with no load) and 6.99 mV for 

DDR3L/DDR3L-RS (with no load).

O

A

CFG[17:0]

Configuration Signals:
The CFG signals have a default value of '1' if not terminated on the 

board. 

• CFG[1:0]: Reserved configuration lane. A test point may be 

placed on the board for this lane.

• CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.

— 1 = Normal operation

— 0 = Lane numbers reversed

• CFG[3]: Reserved
• CFG[4]: eDP enable

— 1 = Disabled

— 0 = Enabled

• CFG[6:5]: PCI Express* Bifurcation: 

— 00 = 1 x8, 2 x4 PCI Express*

— 01 = reserved

— 10 = 2 x8 PCI Express*

— 11 = 1 x16 PCI Express*

• CFG[17:7]: Reserved configuration lanes. A test point may be 

placed on the board for these pins.

I

CMOS

PM_SYNC

Power Management Sync: A sideband signal to communicate 

power management status from the platform to the processor.

I

CMOS

RESET#

Platform Reset pin driven by the PCH.

I 

CMOS

RSVD

RSVD_TP

RSVD_NCTF

Reserved: All signals that are RSVD and RSVD_NCTF must be left 

unconnected on the board. However, Intel recommends that all 

RSVD_TP signals have via test points.

No Connect

Test Point

Non-Critical to 

Function

SM_DRAMRST#

DDR3 DRAM Reset: Reset signal from processor to DRAM devices. 

One common to all channels.

O

CMOS