Spire Jewel 400W SP-ATX-400W-PFC User Manual
Product codes
SP-ATX-400W-PFC
Version:A/0 Page 10 of 17
Spire Corp.
Http://www.spirepower.com & Http://www.spirecoolers.com
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2.2.11 Voltage Hold-up Time
All output will stay within regulation for at least 16ms after an AC line voltage
failure is detected at nominal line (230VAC) under full load condition.
failure is detected at nominal line (230VAC) under full load condition.
2.3 Timing / Housekeeping / Control
Figure 2. Power Supply Timing
2.3.1 PWR_OK
The power supply accepts a logic collector level which will disable/enable
all the output voltages. As the logic level is low, output voltages are enable;
As the logic level is high, output voltages are disable. The definition of
logic low/high level is as:
High Level: 2.50V ~ 5.25V while sourcing 0.4mA maximum
Low Level: 0.0V ~ 0.50V while sinking 5.0mA maximum
Rise Time: 3.0ms maximum (10.0% ~ 90.0%)
all the output voltages. As the logic level is low, output voltages are enable;
As the logic level is high, output voltages are disable. The definition of
logic low/high level is as:
High Level: 2.50V ~ 5.25V while sourcing 0.4mA maximum
Low Level: 0.0V ~ 0.50V while sinking 5.0mA maximum
Rise Time: 3.0ms maximum (10.0% ~ 90.0%)
~
~
~
~
VAC_ON
VAC_OFF
PS_ON#
PS_OFF#
95%
10%
PWR_OK
+12VDC
+5VDC O/P’s
+3.3VDC
T1
T2
T3
T4
T5
T6
PWR_OK Sense Level=95% of nominal
T1 ＜ 100ms
0.1ms ≦ T2 ≦ 25ms
100ms ＜ T3 ＜ 500ms
T4 ≦ 10ms
T5 ≧ 16ms
T6 ≧ 1ms
T1：Power-on Time
T2：Rise Time
T3：PWR_OK Delay
T4：PWR_OK Risetime
T5：AC Loss to PWR_OK Hold-up Time
T6：Power-down Warning