Intel G1620T CM8063701448300 User Manual
Product codes
CM8063701448300
PCU – Serial Peripheral Interface (SPI)
1034
Datasheet
JEDEC ID
Since each serial Flash device may have unique capabilities and commands, the JEDEC
ID is the necessary mechanism for identifying the device so the uniqueness of the
device can be comprehended by the controller (master). The JEDEC ID uses the opcode
9Fh and a specified implementation and usage model. This JEDEC Standard
Manufacturer and Device ID read method is defined in Standard JESD21-C, PRN03-NV.
ID is the necessary mechanism for identifying the device so the uniqueness of the
device can be comprehended by the controller (master). The JEDEC ID uses the opcode
9Fh and a specified implementation and usage model. This JEDEC Standard
Manufacturer and Device ID read method is defined in Standard JESD21-C, PRN03-NV.
Error Correction & Detection
If the first 8 bits specify an opcode which is not supported the slave will not respond
and wait for the next high to low transition on PCU_SPI_CS[1:0]#. The SPI controller
should automatically discard 8 bit words that were not completely received upon de-
assertion of the signal.
and wait for the next high to low transition on PCU_SPI_CS[1:0]#. The SPI controller
should automatically discard 8 bit words that were not completely received upon de-
assertion of the signal.
Any other error correction or detection mechanisms must be implemented in firmware
and/or software.
and/or software.
20.2.6
Multiple Page Write Usage Model
The BIOS and Trusted Execution Engine firmware usage models require that the serial
Flash device support multiple writes to a page (minimum of 512 writes) without
requiring a preceding erase command. The BIOS commonly uses capabilities such as
counters that are used for error logging and system boot progress logging. These
counters are typically implemented by using byte-writes to ‘increment’ the bits within a
Flash device support multiple writes to a page (minimum of 512 writes) without
requiring a preceding erase command. The BIOS commonly uses capabilities such as
counters that are used for error logging and system boot progress logging. These
counters are typically implemented by using byte-writes to ‘increment’ the bits within a
Figure 25. Dual Output Fast Read Timing
PCU_SPI_CS#
PCU_SPI_MOSI
PCU_SPI_MISO
PCU_SPI_CLK
23
22
21
2
1
0
0
1
2
3
4
5
6
7
8
9
10
29
30
31
Dual Output Fast Read
Opcode = 3Bh
24-bit address
PCU_SPI_CS#
PCU_SPI_MOSI
PCU_SPI_MISO
PCU_SPI_CLK
6
4
2
4
2
0
32
33
34
35
36
37
38
39
Dummy Byte
40
41
42
43
44
45
46
47
0
6
7
5
3
5
3
1
1
7
Read Data
Byte 0
Read Data
Byte 1
6
4
2
4
2
0
0
6
7
5
3
5
3
1
1
7
Read Data
Byte 2
Read Data
Byte 3
48
49
50
51
52
53
54
55
MOSI switches from
input to output